Modern digital circuits now incorporate ever larger arrays of circuit elements (RAMs, ROMs CAMs, FIFOs and Random Logic blocks, for example) as designers strive to provide increased circuit functionality. The increasing density of modern digital circuits has greatly increased the difficulty of testing such circuits with conventional external testing machines designed for this purpose. Consequently, much effort has been devoted to designing individual circuit elements with an ability to test themselves, that is, provide the elements with a Built-in Self-Test (BIST) capability. Examples of circuit elements having BIST capability are found in U.S. Pat. No. 4,872,168, issued on Oct. 3, 1989, and U.S. Pat. No. 5,091,908, issued on Feb. 25, 1992, both assigned to AT&T Bell Laboratories, the present assignee.
The presence of individual circuit elements having BIST capability within a Very Large Scale Integrated (VLSI) circuit has not, however, eliminated the difficulty of testing. The testing of a VLSI circuit incorporating a variety of BIST'd elements, that is, elements having BIST capability, requires that an interface be provided within the circuit to couple a control signal from a test controller to each BIST'd element to initiate self-testing. In addition, the interface also must serve to latch a test signature generated by each BIST'd element at the completion of testing to allow subsequent transfer of the signature to the test controller.
One approach to providing such an interface for BIST'd RAM elements is described in the paper "ASIC Implementation of Boundary-Scan and BIST" by H. N. Scholz et al., published in the Proceedings of the 8th International Custom Microelectronics Conference (London, United Kingdom) 1989, pp. 43.1-43.9. In this paper, Scholz et al. describe a Built-In Self-Test (BIST) Resource Interface Controller (BRIC), typically a finite-state machine, for initiating self-testing of an individual BIST'd RAM in response to a start signal from a test controller. At the completion of testing, the RAM generates a test signature, indicative of the test result, which is stored (i.e., latched) in the BRIC.
The disadvantage of this approach is that a separate BRIC is required for each BIST'd RAM. Thus, scheduling of self-testing of each BIST'd RAM by its corresponding BRIC, as well as collection of the test signature from the corresponding BRIC must be coordinated by a test controller. As a result, the test controller must possess a high degree of sophistication to carry out such tasks, thus increasing its complexity and cost.
Thus, there is a need for a built-in self-test control network for scheduling the self-testing of a plurality of different types of BIST'd elements, and for latching the collective test signatures of the elements so as to reduce the complexity of the test controller.